CS302-Digital Logic and Design
Solved MCQS for Final terms papers
Solved by Abid Ali and Team
AL-JUAID INSTITUTE GROUP
1. The terminal count of a 4-bit binary counter in the UP mode is .
a. 1100
b. 0011
c. 1111
d. 0000
2. For a down counter that counts from (111 to 000). If current state is “101” the next state will
be .
a. 111
b. 110
c. 010
d. None of given options
3. The n flip-flops store states.
a. 1
b. 2^n
c. 0
d. 2^(n+1)
4. An Asynchronous Down-counter is implemented (using J-K flip-flop) by connecting
.
a. Q output of all flip-flops to clock input of next flip-flops
b. Q’ output of all flip-flops to clock input of next flip-flops
c. Q output of all flip-flops to J input of next flip-flops
d. Q’ output of all flip-flops to K input of next flip-flops
5. In case of cascading Integrated Circuit counters, the enable inputs and RCOof the Integrated
Circuit counters allow cascading of multiple counters together.
a. True
b. False
6. A decade counter can be implemented by truncating the counting sequence of a MOD-20
counter.
a. True
b. False
7. The 74HC163 is a 4-bit Synchronous Counter, it has data output pins.
a. 2
b. 4
c. 6
d. 8
8. Counters as the name indicates are not triggered simultaneously
a. Asynchronous
b. Synchronous
c. Positive-Edge triggered
d. Negative-Edge triggered
9. Divide-by-32 counter can be achieved by using
a. Flip-Flop and DIV 10
b. Flip-Flop and DIV 16
c. Flip-Flop and DIV 32
d. DIV 16 and DIV 32
10. The input overrides the input
a. Asynchronous, synchronous
b. Synchronous, asynchronous
c. Preset input (PRE), Clear input (CLR)
d. Clear input (CLR), Preset input (PRE)
11. The synchronous counters are also known as Ripple Counters:
a. True
b. False
12. Each stage of Master-slave flip-flop works at of the clock signal
a. Each stage works on complete clock signal
b. One fourth
c. One third
d. One half
13. With a 100 KHz clock frequency, eight bits can be serially entered into a shift register in
a. 80 micro seconds
b. 8 micro seconds
c. 80 mili seconds
d. 10 micro seconds
14. Number of states in an 8-bit Johnson counter sequence are:
a. 8
b. 12
c. 14
d. 16
15. A synchronous decade counter will have flip-flops
a. 3
b. 4
c. 7
d. 10
16. is one of the examples of synchronous inputs.
a. J-K input
b. EN input
c. Preset input (PRE)
d. Clear input (CLR)
AL-JUAID INSTITUTE GROUP
17. A decade counter is
a. Mod-3 counter
b. Mod-5 counter
c. Mod-8 counter
d. Mod-10 counter
18. is said to occur when multiple internal variables change due to change in one input
variable
a. Hold and Wait
b. Clock Skew
c. Race condition
d. Hold delay
19. In moore machine the output depends on
a. The current state and the output of previous flip flop
b. Only inputs
c. The current state
d. The current state and inputs
20. Asynchronous mean that
a. Each flip-flop after the first one is enabled by the output of the preceding flip-flop
b. Each flip-flop is enabled by the output of the preceding flip-flop
c. Each flip-flop except the last one is enabled by the output of the preceding flip-flop
d. Each alternative flip-flop after the first one is enabled by the output of the preceding
flip-flop
21. Bi-stable devices remain in either of their states unless the inputs force the device to
switch its state
a. Ten
b. Eight
c. Three
d. Two
22. A counter is implemented using three (3) flip-flops, possibly it will have maximum
output status.
a. 3
b. 7
c. 8
d. 15
23. According to moore circuit, the output of synchronous sequential circuit depend/s on
of flip flop.
a. Previous state
b. Present state
c. Next state
d. External inputs
24. In gated SR latch, what is the value of the output if EN=1, S=0 and R=1?
a. Qt
b. 0
c. 1
d. Invalid
AL-JUAID INSTITUTE GROUP
25. A Divide-by-20 counter can be achieved by using
a. Flip-Flop and DIV 10
b. Flip-Flop and DIV 16
c. Flip-Flop and DIV 32
d. DIV 10 and DIV 16
26. We have a digital circuit. Different parts of circuit operate at different clock frequencies
(4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency
(4MHZ), to supply the required frequency to each part of circuit, we can get help by using
.
a. Using S-R Flop-Flop
b. D-flipflop
c. J-K flip-flop
d. T-Flip-Flop
27. A one-shot mono-stable device contains _
a. AND gate, Resistor, Capacitor and NOT Gate
b. NAND gate, Resistor, Capacitor and NOT Gate
c. NOR gate, Resistor, Capacitor and NOT Gate
d. XNOR gate, Resistor, Capacitor and NOT Gate
28. The inputs can be directly mapped to karnaugh maps.
a. S-R
b. J-K
c. Flip-Flop
d. External
29. A mono-stable device only has a single stable state
a. True
b. False
30. The minimum time required for the input logic levels to remain stable before the clock
transition occurs is known as the
a. Set-up time
b. Hold time
c. Pulse interval time
d. Pulse stability time (PST)
31. The low to high or high to low transition of the clock is considered to be a(n)
a. State
b. Edge
c. Trigger
d. One-shot
32. A 4-bit UP/DOWN counter is in DOWN mode and in the 1010 state, on the next clock pulse,
to what state does the counter go?
a. 1001
b. 1011
c. 0011
d. 1100
AL-JUAID INSTITUTE GROUP
33. When the Hz sampling interval is selected, the signal at the output of the J-K flip-flop
has a time period of seconds.
a. 1, 2
b. 0, 2
c. 2, 5
d. 1, 1
34. Assume a J-K flip-flop has 1s on the J and K inputs. The next clock pulse will cause the
output to .
a. Set
b. Toggle
c. Latch
d. Reset
35. A stage in the shift register consists of
a. A latch
b. A flip flop
c. A byte of storage
d. Four bits of storage
36. When the both inputs of edge-triggered J-K flop-flop are set to logic zero
a. The flop-flop is triggered
b. Q=0 and Q’=1
c. Q=1 and Q’=0
d. The output of flip-flop remains unchanged
37. A positive edge-triggered flip-flop changes its state when
a. Enable input (EN) is set
b. Preset input (PRE) is set
c. Low-to-high transition of clock
d. High-to-low transition of clock
38. If a circuit suffers “Clock Skew” problem, the output of circuit can’t be guarantied.
a. True
b. False
39. The minimum time for which the input signal has to be maintained at the input of flip-flop is
called of the flip-flop.
a. Set-up time
b. Hold time
c. Pulse interval time
d. Pulse stability time (PST)
40. A modulus-14 counter has fourteen states requiring
a. 14 flip flops
b. 14 registers
c. 4 flip flops
d. 4 registers
41. In Master-Slave flip-flop the clock signal is connected to slave flip-flop using gate.
a. AND
b. OR
c. NOT
c. NAND
AL-JUAID INSTITUTE GROUP
42. flip-flops are obsolete now.
a. Edge-triggered
b. Master-Slave
c. T-flipflop
d. D-flipflop
43. The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip
flop
a. Doesn’t have an invalid state
b. Sets to clear when both J=0 and K=0
c. It does not show transition on change in pulse
d. It does not accept asynchronous inputs
44. The glitches due to “Race Condition” can be avoided by using a .
a. Gated flip-flops
b. Pulse triggered flip-flops
c. Positive-Edge triggered flip-flops
d. Negative-Edge triggered flip-flops
45. For a gated D-Latch if EN=1 and D=1 then Q(t+1)=
a. 0
b. 1
c. Q(t)
d. Invalid
46. occurs when the same clock signal arrives at different times at different clock
inputs due to propagation delay.
a. Race condition
b. Clock skew
c. Ripple effect
d. None of given options
47. In a 4-bit binary counter, the next state after the terminal count in the DOWN mode is
a. 0000
b. 1111
c. 0001
d. 10000
48. A 4-bit binary UP/DOWN counter is in the binary state zero, the next state in the DOWN
mode is
a. 0001
b. 1111
c. 1000
d. 1110
49. An Astable multivibrator is known as a(n) .
a. Oscillator
b. Booster
c. One-shot
AL-JUAID INSTITUTE GROUP
d. Dual-shot
50. is one of the examples of asynchronous inputs.
a. J-K input
b. S-R input
c. D input
d. Clear input (CLR)
51. In Master-Slave flip-flop setup, the master flip-flop operators at
a. Positive half cycle of pulse
b. Negative half cycle of pulse
c. Both Master-Slave operator simultaneously
d. Master-Slave flip-flop does not operate on pulses rather it is edge triggered
52. The power consumed by a flip-flop is defined by _
a. P = Icc x Rcc
b. P = Vcc x Rcc
c. P = Vcc x Icc
d. P = Mcc x Vcc
53. In designing any counter the transition from a current state to the next state is determined by
a. Current state and inputs
b. Only inputs
c. Only current state
d. Current state and outputs
54. The 74HC163 is a 4-bit Synchronous Counter, it has parallel data inputs pins
a. 2
b. 4
c. 6
d. 8
55. The 3-bit up counter can be implemented using flip-flop(s).
a. S-R flip-flops only
b. S-R flip-flops and D-flip-flops
c. S-R flip-flops or D-flip-flops
d. D-flip-flop only
56. The terminal count of a modulus-13 binary counter is
a. 0000
b. 1111
c. 1101
d. 1100
57. The terminal count of a 4-bit binary counter in the DOWN mode is
a. 0000
b. 0011
c. 1100
d. 1111
58. In gated SR latch, what is the value of the output if EN=1, S=1 and R=0?
a. Qt
b. 0
c. 1
d. Invalid
59. In gated SR latch, what is the value of the output if EN=1, S=0 and R=0?
a. Qt
b. 0
c. 1
d. Invalid
60. Which mechanism allocate the binary values to the states in order to reduce the cost of the
combinational circuits?
a. State reduction
b. State minimization
c. State assignment
d. State evaluation
61. State of flip-flop can be switched by changing its
a. Input signal
b. Output signal
c. Momentary signal
d. Contemporary signal
62. Once the state diagram is drawn for any sequential circuit the next step is to draw
a. Transiation table
b. Karnaugh map
c. Next-state table
d. Logic expression
63. Design of state diagram is one of many steps used to design
a. A clock
b. A truncated counter
c. An UP/DOWN counter
d. Any counter
64. Flip flops are also called
a. Bi-stable multivibrators
b. Bi-stable singlevibrators
c. Bi-stable dualvibrators
d. Bi-stable transformer
65. Three cascaded modulus-10 counters have an overall modulus of
a. 30
b. 100
c. 1000
d. 10000
66. In mealy machine the output depends on
a. The inputs
b. The current state
c. Current state and the inputs
AL-JUNAID INSTITUTE GROUP
d. None of the above
67. If S=1 and R=0, then for positive edge triggered flipflop Q(t+1) =
a. 0
b.1
c. Invalid
d. Input is invalid
68. The term hold always means . a. Q=0, Q’=1
b. Q=1, Q’=0
c. Q=0, Q’=0
d. No change
69. A transparent mode means
a. The changes in the data at the inputs of the latch are seen at the output
b. The changes in the data at the inputs of the latch are not seen at the output
c. Propagation delay is zero (output is immediately changed when clock signal
is applied)
d. Input hold time is zero (no need to maintain input after clock ttransition)
70. A flip-flop is presently in SET state and must remain SET on the next clock pulse.
What must j and k be?
a. J=1, K=0
b. J=1,
K=X(Don’tcare)
c.J=X(Don’tcare),K=0
d. J=0, K=X(Don’t care)
71. To parallel load a byte of data into a shift register, there must
be
a. One clock pulse
b. One clock pulse for each 1 in the data
c. Eight clock pulse
d. One clock pulse for each 0 in the data
Question No: 1
A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will
be required to shift the value completely out of the register.
► 1
► 2
► 4
► 8 (Page 356)
Question No: 2
In a sequential circuit the next state is determined by ________ and _______
AL-JUNAID INSTITUTE GROUP
► State variable, current state
► State variable, current state
► Current state and external input (Page 318)
► Input and clock signal applied
Question No: 3
The divide-by-60 counter in digital clock is implemented by using two cascading counters:
► Mod-6, Mod-10 (Page 299)
► Mod-50, Mod-10
► Mod-10, Mod-50
► Mod-50, Mod-6
Question No: 4
In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output
state is maintained.
► True (Page 221)
► False
Question No: 5
The minimum time for which the input signal has to be maintained at the input of flip-flop
is called ______ of the flip-flop.
► Set-up time
► Hold time (Page 242)
► Pulse Interval time
► Pulse Stability time (PST)
Question No: 6
74HC163 has two enable input pins which are _______ and _________
► ENP, ENT (Page 285)
► ENI, ENC
► ENP, ENC
► ENT, ENI
Question No: 7
____________ is said to occur when multiple internal variables change due to change in one
input variable
► Clock Skew
► Race condition (Page 267)
► Hold delay
► Hold and Wait
Question No: 8
The _____________ input overrides the ________ input
► Asynchronous, synchronous (Page 369)
► Synchronous, asynchronous
AL-JUNAID INSTITUTE GROUP
► Preset input (PRE), Clear input (CLR)
► Clear input (CLR), Preset input (PRE)
Question No: 9
A decade counter is __________.
► Mod-3 counter
► Mod-5 counter
► Mod-8 counter
► Mod-10 counter (Page 274)
Question No: 10
In asynchronous transmission when the transmission line is idle, ________
► It is set to logic low
► It is set to logic high (Page 356)
► Remains in previous state
► State of transmission line is not used to start transmission
Question No: 11
A Nibble consists of _____ bits
► 2
► 4 (Page 394)
► 8
► 16
Question No: 12
The output of this circuit is always ________.
► 1
► 0
► A
Question No: 13
Excess-8 code assigns _______ to “-8”
► 1110
► 1100
► 1000
► 0000 (Page 34)
Question No: 14
The voltage gain of the Inverting Amplifier is given by the relation _______
► Vout / Vin = - Rf / Ri (Page 446)
► Vout / Rf = - Vin / Ri
► Rf / Vin = - Ri / Vout
► Rf / Vin = Ri / Vout
Question No: 15
LUT is acronym for _________
► Look Up Table (Page 439)
► Local User Terminal
► Least Upper Time Period
► None of given options
Question No: 16
The three fundamental gates are ___________
► AND, NAND, XOR
► OR, AND, NAND
► NOT, NOR, XOR
► NOT, OR, AND (Page 40)
Question No: 17
The total amount of memory that is supported by any digital system depends upon _____
► The organization of memory
►The structure of memory
► The size of decoding unit
► The size of the address bus of the microprocessor (Page 430)
Question No: 18
Stack is an acronym for ________
► FIFO memory
► LIFO memory (Page 429)
► Flash Memory
► Bust Flash Memory
Question No: 19
Addition of two octal numbers “36” and “71” results in ________
► 213
► 123
► 127
► 345
Question No: 20
__________ is one of the examples of synchronous inputs.
► J-K input (Page 235)
► EN input
► Preset input (PRE)
► Clear Input (CLR)
Question No: 21
AL-JUNAID INSTITUTE GROUP
__________occurs when the same clock signal arrives at different times at different clock
inputs due to
propagation delay.
► Race
► Clock Skew (Page 226)
► Ripple Effect
► None of given option
Question No: 22
Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the
counter counts upward (0000 to 1111) and if external input (X) is “1” the counter counts
downward (1111 to 0000), now suppose that the present state is “1100” and X=1, the next
state of the counter will be ___________
► 0000
► 1101
► 1011
► 1111
Question No: 23
In a state diagram, the transition from a current state to the next state is determined by
► Current state and the inputs (Page 332)
► Current state and outputs
► Previous state and inputs
► Previous state and outputs
Question No: 24
________ is used to simplify the circuit that determines the next state.
► State diagram
► Next state table
► State reduction
► State assignment (Page 335)
Question No: 25
A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will
be required to shift the value completely out of the register.
► 1
► 2
► 4
► 8 (Page 356)
Question No: 26
Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the
nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit
first.)
► 1100
► 0011
► 0000
► 1111
Question No: 27
The ANSI/IEEE Standard 754 defines a __________Single-Precision Floating Point format
for binary numbers.
► 8-bit
► 16-bit
► 32-bit
► 64-bit
Question No: 28
The decimal “17” in BCD will be represented as _________
► 11101
► 11011
► 10111
► 11110
Question No: 29
The basic building block for a logical circuit is _______
► A Flip-Flop
► A Logical Gate
► An Adder
► None of given options
Question No: 30
The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1.
► Undefined
► One
► Zero
► No Output as input is invalid.
Question No: 31
________ is invalid number of cells in a single group formed by the adjacent cells in K-map
► 2
► 8
► 12
► 16
Question No: 32
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flipflop ___________
► Doesn’t have an invalid state (Page 232)
► Sets to clear when both J = 0 and K = 0
► It does not show transition on change in pulse
► It does not accept asynchronous inputs
Question No: 33
A GAL is essentially a ________.
► Non-reprogrammable PAL
► PAL that is programmed only by the manufacturer
► Very large PAL
► Reprogrammable PAL (Page 183)
Question No: 34
In ____________, all the columns in the same row are either read or written.
► Sequential Access
► MOS Access
► FAST Mode Page Access (Page 413)
► None of given option
Question No: 35
The PROM consists of a fixed non-programmable ____________ Gate array configured as
a decoder.
► AND
► OR
► NOT
► XOR
Question No: 36
In order to synchronize two devices that consume and produce data at different rates, we
can use _________
► Read Only Memory
► Fist In First Out Memory (Page 425)
► Flash Memory
► Fast Page Access Mode Memor
Question No: 37
___________ is one of the examples of synchronous inputs.
► J-K input
► EN input
► Preset input (PRE)
► Clear Input (CLR)
Question No: 38
A positive edge-triggered flip-flop changes its state when ________________
► Low-to-high transition of clock (Page 228)
► High-to-low transition of clock
► Enable input (EN) is set
► Preset input (PRE) is set
Question No: 39
___________ is one of the examples of asynchronous inputs.
► J-K input
► S-R input
► D input
► Clear Input (CLR)
Question No: 40
A frequency counter ______________
► Counts pulse width
► Counts no. of clock pulses in 1 second (Page 301)
► Counts high and low range of given clock pulse
► None of given options
Question No: 41
The _____________ input overrides the ________ input
► Asynchronous, synchronous
► Synchronous, asynchronous
► Preset input (PRE), Clear input (CLR)
► Clear input (CLR), Preset input (PRE)
Question No: 42
In a sequential circuit the next state is determined by ________ and _______
► State variable, current state
► Current state, flip-flop output
► Current state and external input
► Input and clock signal applied (Page 305)
Question No: 43
__________occurs when the same clock signal arrives at different times at different clock
inputs due to propagation delay.
► Race condition
► Clock Skew
► Ripple Effect
► Ripple Effect
► None of given options
Question No: 44
Flip flops are also called _____________
► Bi-stable dualvibrators
► Bi-stable transformer
► Bi-stable multivibrators (Page 228)
► Bi-stable singlevibrators
Question No: 45
The address from which the data is read, is provided by _______
► Depends on circuitry
► None of given options
► RAM
► Microprocessor
Question No: 46
74HC163 has two enable input pins which are _______ and _________
► ENP, ENT (Page 285)
► ENI, ENC
► ENP, ENC
► ENT, ENI
Question No: 47
One
Above is the circuit diagram of _______.
► Asynchronous up-counter
► Asynchronous down-counter
► Synchronous up-counter
► Synchronous down-counter
Question No: 48
___________ is said to occur when multiple internal variables change due to change in one
input variable
► Clock Skew
► Race condition (Page 267)
► Hold delay
► Hold and Wait
Question No: 49
The sequence of states that are implemented by a n-bit Johnson counter is
► n+2 (n plus 2)
► 2n (n multiplied by 2)
► 2n
(2 raise to power n)
► n2 (n raise to power 2)
Question No: 50
Given the state diagram of an up/down counter, we can find ________
► The next state of a given present state (Page 371)
► The previous state of a given present state
► Both the next and previous states of a given state
► The state diagram shows only the inputs/outputs of a given states
Question No: 51
A logic circuit with an output X = A B C+ A Bconsists of ________.
► two AND gates, two OR gates, two inverters
► three AND gates, two OR gates, one inverter
► two AND gates, one OR gate, two inverters (Lecture 8)
► two AND gates, one OR gate
Question No: 52
A decade counter is __________.
► Mod-3 counter
► Mod-5 counter
► Mod-8 counter
► Mod-10 counter (Page 274)
Question No: 53
A Nibble consists of _____ bits
► 2
► 4 (Page 394)
► 8
► 16
Question No: 54
DRAM stands for __________
► Dynamic RAM (Page 407)
► Data RAM
► Demoduler RAM
► None of given options
Question No: 55
The three fundamental gates are ___________
► AND, NAND, XOR
► OR, AND, NAND
► NOT, NOR, XOR
► NOT, OR, AND (Page 40)
Question No: 56
The expression F=A+B+C describes the operation of three bits _____ Gate.
► OR (Page 42)
► AND
► NOT
► NAND
Question No: 57
Stack is an acronym for_________
► FIFO memory
► LIFO memory (Page 429) rep I think so
► Flash Memory
► Bust Flash Memory
Question No: 58
The ANSI/IEEE Standard 754 defines a __________Single-Precision Floating Point format
for binary numbers.
► 8-bit
► 16-bit
► 32-bit (Page 25)
► 64-bit
Question No: 59
The decimal “17” in BCD will be represented as _________
► 11101
► 11011
► 10111 (According to rule)
► 11110
Question No: 60
The basic building block for a logical circuit is _______
► A Flip-Flop
► A Logical Gate (Page 7)
► An Adder
► None of given options
Question No: 61
The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1.
► Undefined
► One
► Zero (According to rule)
► No Output as input is invalid.
Question No: 62
________ is invalid number of cells in a single group formed by the adjacent cells in K-map
► 2
► 8
► 12 (According to rule “2^n”)
► 16
Question No: 63
The PROM consists of a fixed non-programmable ____________ Gate array configured as
a decoder.
► AND (Page 182)
► OR
► NOT
► XOR
Question No: 64
_________ is one of the examples of asynchronous inputs.
► J-K input
► S-R input
► D input
► Clear Input (CLR) (Page 235)
Question No: 65
The basic building block for a logical circuit is _______
► A Flip-Flop
► A Logical Gate (Page 7)
► An Adder
► None of given options
Question No: 66
The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1.
► Undefined
► One
► Zero (According to rule) rep
► No Output as input is invalid.
Question No: 67
________ is invalid number of cells in a single group formed by the adjacent cells in K-map
► 2
► 8
► 12 (According to rule “2^n” ) req
► 16
Question No: 68
The PROM consists of a fixed non-programmable ____________ Gate array configured as
a decoder.
► AND (Page 182)
► OR
► NOT
► XOR
Question No: 69
In a state diagram, the transition from a current state to the next state is determined by
► Current state and the inputs (Page 232)
► Current state and outputs
► Previous state and inputs
► Previous state and outputs
Question No: 70
_______ is used to simplify the circuit that determines the next state.
► State diagram
► Next state table
► State reduction
► State assignment (Page 335)
Question No: 71
________ is used to minimize the possible no. of states of a circuit.
► State assignment (Page 341)
► State reduction
► Next state table
► State diagram
Question No: 72
5-bit Johnson counter sequences through ____ states
► 7
► 10 (Page 354)
► 32
► 25
Question No: 73
The address from which the data is read, is provided by _______
► Depends on circuitry
► None of given options
► RAM
► Microprocessor (Page 397)
Question No: 74
Demultiplexer is also called ----------------
► Data selector
► Data router
► Data distributor (Page 178)
► Data encoder
Question No: 75
A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the
power dissipation of the flip-flop is b
► 10 mW
► 25 mW (Page 242)
► 64 mW
► 1024
AL-JUNAID INSTITUTE GROUP
Question No: 76
The 4-bit 2‟s complement representation of “+5” is _____________
► 1010
► 1110
► 1011
► 0101 (Page 22)
Question No: 77
The storage cell in SRAM is
► a flip –flop
► a capacitor (Page 407)
► a fuse
► a magnetic domain
Question No: 78
What is the difference between a D latch and a D flip-flop?
► The D latch has a clock input.
► The D flip-flop has an enable input.
► The D latch is used for faster operation.
►The D flip-flop has a clock input. (For Google)
Question No: 79
The OR gate performs Boolean ___________.
► multiplication
► subtraction
► division
► addition (Page 42)
Question No: 80
Determine the values of A, B, C, and D that make the sum term A(bar) + B+C(bar)+D
equal to zero.
► A = 1, B = 0, C = 0, D = 0
► A = 1, B = 0, C = 1, D = 0 (Lecture 8)
► A = 0, B = 1, C = 0, D = 0
►A = 1, B = 0, C = 1, D = 1
Question No: 81
A Karnaugh map is similar to a truth table because it presents all the possible values of
input variables and the resulting output of each value.
►True
►False
Question No: 82
NOR Gate can be used to perform the operation of AND, OR and NOT Gate
AL-JUNAID INSTITUTE GROUP
►True (Page 50)
►False
Question No: 83
Using multiplexer as parallel to serial converter requires ___________ connected to the
multiplexer
►A parallel to serial converter circuit (Page 244)
►A counter circuit
►A BCD to Decimal decoder
►A 2-to-8 bit decoder
Question No: 84
In designing any counter the transition from a current state to the next sate is determined
by---------
►Current state and inputs (Page 332)
►Only inputs
►Only current state
►current state and outputs
Question No: 85
Sum term (Max term) is implemented using ________ gates ..
►OR (Page 78)
►AND
►NOT
►OR-AND
Question No: 86
If S=1 and R=0, then Q (t+1) = _________ for positive edge triggered flip-flop
►0
►1 (Page 230)
►Invalid
►Input is invalid
Question No: 87
If S=1 and R=1, then Q (t+1) = _________ for negative edge triggered flip-flop
► 0
► 1
► Invalid (Page 233)
► Input is invalid
Question No: 88
If the FIFO Memory output is already filled with data then ________
► It is locked; no data is allowed to enter
► It is not locked; the new data overwrites the previous data.
► Previous data is swapped out of memory and new data enters
► None of given options
Question No: 89
In ________ Q output of the last flip-flop of the shift register is connected to the data input
of the first flip-flop of the shift register.
►Moore machine
►Meally machine
►Johnson counter
►Ring counter (Page 355)
Question No: 90
A synchronous decade counter will have _______ flip-flops
► 3
► 4 (Page 281)
► 7
► 10
Question No: 91
A positive edge-triggered flip-flop changes its state when ________________
► Low-to-high transition of clock (Page 228)
► High-to-low transition of clock
► Enable input (EN) is set
► Preset input (PRE) is set
Question No: 92
A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE
USER AND NOT BY THE MANUFACTURER.
► TRUE (Page 182)
► FALSE
Question No: 93
A particular half adder has
► 2 INPUTS AND 1 OUTPUT
► 2 INPUTS AND 2 OUTPUT (Page 134)
► 3 INPUTS AND 1 OUTPUT
► 3 INPUTS AND 2 OUTPUT
Question No: 94
NOR gate is formed by connecting _________
► OR Gate and then NOT Gate (Page 47)
► NOT Gate and then OR Gate
► AND Gate and then OR Gate
► OR Gate and then AND Gate
Question No: 95
AL-JUNAID INSTITUTE GROUP
Smallest unit of binary data is a ________
► Bit (Page 394)
► Nibble
► Byte
► Word
Question No: 96
In ________ outputs depend only on the current state.
► Mealy machine
► Moore Machine (Page 332)
► State Reduction table
► State Assignment table
Question No: 97
RCO Stands for _________
► Reconfiguration Counter Output
► Reconfiguration Clock Output
► Ripple Counter Output
► Ripple Clock Output (Page 285)
Question No: 98
A positive edge-triggered flip-flop changes its state when ________________
► Low-to-high transition of clock (Page 228)
► High-to-low transition of clock
► Enable input (EN) is set
► Preset input (PRE) is set
Question No: 99
The low to high or high to low transition of the clock is considered to be a(n) ________
► State
► Edge (Page 228)
► Trigger
► One-shot
Question No: 100
If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop
► 0
► 1 (Page 230) req
► Invalid
► Input is invalid
Question No: 101
The Decimal “8”is represented as _________ using Gray-Code.
►0011
►1100
►1000
►1010
Question No: 102
The simplest of the Encoder are the _______ Encoder.
►2n-1 - to – n
►n – to- 2n
►2n -to-n
►n-to- 2n-1
Question No: 103
Using multiplexer as parallel to series Converter requires_______ Connected to the
multiplexer.
► A parallel series converter Circuit
►A Counter circuit
► A BCD to Decimal Decoder
► A 2 – to-8 bit Decoder
Question No: 104
74HC163 has two enable inputs pins which are _______ and _______.
► ENP, ENT
►ENI, ENC
►ENP, ENC
►ENT, ENI
Question No:
Given the sate diagram of an up/down counter, we can find_______.
► The Next State of given present state.
►The Previous state of given present state.
► Both the Next and previous state of given present state.
► The state diagram show only the input/output of a given.
Question No: 105
A 4-bit a parallel in / serial out shift register contain the value of “0100”,
______ clock signal(s) will be required to the shift the value completely out of
register (I. e. to set the register to 0).
►1
►2
►3
►4
Question No: 106
The 2 complement method is used to _______.
►Convert binary number to decimal.
►Convert decimal number to binary.
►Represent singed number.
►Represent positive number.
Question No: 107
1011 – 101 = _______.
Note: both values are in binary
►1100
►0110
►0011
►1001
Question No: 108
At J=1 and K=1, output of JK Flip-flop will be _______.
►Set
►Reset
►Toggle
►invalid
Question No: 109
Which one 1 is taken as a group on a karnaugh map, the number of variables eliminated
from the output expression is/are_______.
►0
►1
►2
►3
Question No: 110
Using 15 digits (including the sign digit) notation the largest number that can be
represented is ______.
►999,999,999,999 X 10100
►0.999, 999, 999, 999 X 1099
►999,999,999,999 X 1099
►0.999, 999, 999, 999 X 1099
Question No: 110
The _____output of first 74HC163 counter is connected to _____ and _____ input of other
74HC163 Counter to from a single cascaded counter.
►RCO, ENT, ENP
►ENT, RCO, ENP
►ENP, RCO, ENT
►RCO, ENI, ENC
Question No: 111
The sequential circuit whose output depend on the current state and the input knows as
_____.
►Moore Machine
►Mealy Machine
►Counter
►Flip Flop
Question No: 112
The best state assignment tends to _____.
►Maximizes the number of state variables that don’t change in group of
related states
►Minimizes the number of state variables that don’t change in group of related states
►Minimizes the equivalent states
►Maximizes the equivalent states
Question No: 113
In _____ the Q output of the last flip-flop of the shift register is connected to the data input
of the first flip-flop.
►Moore machine
►Mealy machine
►Johnson counter
►Ring counter
Question No: 114
Flip flops are also called_____.
►Bi-stable dualvibrators
►Bi-stable transformer
►Bi-stable Multivibrators
►Bi-stable singlevibratos
Question No: 115
If S=1 and R=0, then Q (t+1) = _____for positive edge triggered flip-flop
►0
►1
►Invalid
►Input is invalid
Question No: 116
__________Flip-Flop are obsolete now,
►Edge- triggered
►Master-Slave
►T-Flip-Flop
►D--Flip-Flop
Question No: 117
Bi-stable devices remain in either of their ________states unless the input force the device
to switch its state.
►Ten
►Eight
►Three
►Two
Question No: 118
The counter states can be determined by the formula _____ (“n” represent the total
number of flip-flop)
►n2 (n rise to power 2)
►n2-1(n raise to power 2 and then minus 1)
►2n (2 raise to power n)
►2n
-1 (2 raise to power n and then minus 1)
Question No: 119
The Sequential circuit, whose output is determined by the current state only is known as
_____
►Moor Machine
►Mealy Machine
►Counter
►Flip Flop
Question No: 120
A GAL is essentially a _____
► Non- reprogrammable PAL
►PAL that is programmed only by the manufacturer
► Reprogrammable PAL
Question No: 121
Which is not characteristic of a shift register?
► Serial in/parallel in
►Serial in / parallel out
►parallel in /serial out
► parallel in/ parallel out
Question No: 122
A Nibble Consists of __________ bits
►2
►4
►8
►16
Question No: 123
Smallest unit of binary data is a_______.
►Bit
►Nibble
►Byte
►Word
Question No: 124
The____ of a ROM is the time its takes for the data to appear at the data Output of the
ROM chip after an address is applied at the address input lines.
►Write Time
►Refresh Time
►Access Time
Question No: 125
In ____________, all the columns in the same row are either read od written.
►Sequential Access
►MOS Access
►FAST Mode page Access
►None of given option
Question No: 126
FIFO is an acronym for________.
►First In, First out
►Fly In, Fly out
►Fast In, Fast out
Question No: 127
If the FIFO Memory output is already filled with date than_______.
►it is locked, no data is allowed to either
►it is not locked, the new data overwrites the previous data.
►Previous data is swapped out of memory and new data enters
►None of given option
Question No: 128
Stack is a_______.
►Bust Flash Memory
►FIFO Memory
►LIFO Memory
►Flash Memory
Question No: 129
A Flash A/D converter uses_______.
►Counters
►Flip-Flop
►Op-amps
►An integrator
Question No: 130
LUT is an acronym for _______.
►Look Up Table
►Local User terminal
►Least Upper Time period
►None of given option
Question No: 131
The process of converting the analogue signal into a digital representation (code) is known
as _______.
►Strobing
►Amplification
►Quantization
►Digitization
Question No: 132
The active high and active low input of 3-to-8 Decoder are as follows.
► one active –high and the remaining two are active - low
►Two active – high and the remaining one is active low
►All active high
►All active low
Question No: 133
GAL is an acronym for _______.
►Generic Analysis Logic
►General Array logic
►Generic Array Logic
Question No: 134
_______Counters as the name indicates are not triggered simultaneously
►Synchronous
►Asynchronous
►Positive- Edge triggered
►Negative- Edge triggered
Question No: 135
____________ is said to occur when multiple internal variables change due to change in one
input variable.
►Race Condition
► Propagation delay
►Ripple effect
►Clock skew
Question No: 136
The power consumed by a flip-flop is defined by__________.
AL-JUNAID INSTITUTE GROUP
►P = Icc X Rcc
►P = Vcc X Rcc
►P = Vcc X Icc
►P = Mcc X Vcc
Question No: 137
The minimum time required for the input logic level to remain stable before the clock
transition occur is known as the __________.
►Pulse Stability time (PST)
►Set- up time
►Hold time
►Pulse Interval time
Question No: 138
When have a digital circuit .Different parts of circuit operate at different frequencies
(4MHZ, 2MHZ, and 1MHZ), but we have a single clock source having a fix clock
frequencies (4MHZ)we can get help by using__________.
►T- Flop-Flop
►S-R Flop-Flop
►D- Flop-Flop
►J-K Flop-Flop
Question No: 139
________ is used to minimize the possible no of states of a cricut.
► State assignment
►State reduction
►Next state table
►State diagram
Question No: 140
“A + B = B + A” is ____________.
►Demorgan Law
►Distributive Law
►Commutative Law
►Associative Law
Question No: 141
The Programmable Array Logic (PAL) has _______AND array and a OR Array
►Fixed, programmable
► programmable, Fixed
► Fixed, Fixed
Question No: 142
The _______Encoder is used as a keypad encoder.
►2-to-8 encoder
►4-to-16 encoder
►BCD-to - Decimal
►Decimal-to-BCD priority
Question No: 143
Given the state diagram of an up/down counter. We can find ____________.
►The next of a given present state
►The previous state of a given present
►Both the next and previous of a given present
Question No: 144
In single – precision Floating point format, “exponent” is represented by ________ bits.
►8-bits
►16-bits
►32- bits
►64 –bits
Question No: 145
A divide – by – 50 counter divides the input ________ signal to a 1Hz signal.
►10 Hz
►50 Hz
►100 Hz
►500 Hz
Question No: 146
In ______all the columns in the same row are either read or written.
►Sequential Access
►MOS Access
►FAST Mode page Access
Question No: 147
A standard POS from has______ terms that all the variables in the domain of the
expression
►Sum
►Min
►Product
Question No: 148
What will be output state when J=1, K=0 and CLR input is active?
►Q=1
►Q=0
Question No: 149
When PRE = 0 and CLR = 1, Qt=0 then Q(t+1) will be ________.
►output of flip-flop will be set (Logic 1)
►output of flip-flop will be reset (Logic 1)
►output of flip-flop will be invalid
►Flip-flop will change output on Clock transition
Question No: 150
Compared to analog systems, digital systems. ________.
►are less prone to noise
►can represent an infinite number of values.
►can handle much higher power
►occupy large space
Question No: 151
The design and implementation of synchronous counters star from ________.
►Truth table
►K-map
►State table
►State diagram
Question No: 152
Invalid state of NOR based SR latch occurs when ________.
►S=0, R=0
►S=0, R=1
►S=1, R=0
►S=1, R=1
72. The terminal count of a 4-bit binary counter in the UP mode is . a. 1100
b. 0011
c. 1111
d. 0000
73. For a down counter that counts from (111 to 000). If current state is “101” the next state
will be .
a. 111
b. 110
c. 010
d. None of given options
74. The n flip-flops store states.
a. 1
b.2^n
c. 0
d. 2^(n+1)
75. An Asynchronous Down-counter is implemented (using J-K flip-flop) by connecting
.
a. Q output of all flip-flops to clock input of next flip-flops
b. Q’ output of all flip-flops to clock input of next flip-flops
c. Q output of all flip-flops to J input of next flip-flops
d. Q’ output of all flip-flops to K input of next flip-flops
76. In case of cascading Integrated Circuit counters, the enable inputs and RCOof the
Integrated Circuit counters allow cascading of multiple counters together.
a. True
b. False
77. A decade counter can be implemented by truncating the counting sequence of a MOD20 counter.
a. True
b.False
78. The 74HC163 is a 4-bit Synchronous Counter, it has data output pins.
a. 2
b.4
e. 6
f. 8
79. Counters as the name indicates are not triggered
simultaneously
a. Asynchronous
e. Synchronous
f. Positive-Edge triggered
g. Negative-Edge triggered
80. Divide-by-32 counter can be achieved by using
a. Flip-Flop and DIV
10
b. Flip-Flop and DIV 16
e. Flip-Flop and DIV 32
f. DIV 16 and DIV 32
81. The input overrides the
input
a. Asynchronous,
synchronous
e. Synchronous, asynchronous
f. Preset input (PRE), Clear input (CLR)
g. Clear input (CLR), Preset input (PRE)
82. The synchronous counters are also known as Ripple Counters:
a. Tr
ue
b.False
83. Each stage of Master-slave flip-flop works at of the clock signal
a. Each stage works on complete clock signal
b. One fourth
c. One
third
d.One half
84. With a 100 KHz clock frequency, eight bits can be serially entered into a shift register
in
a. 80 micro seconds
e. 8 micro seconds
f. 80 mili seconds
g. 10 micro seconds
85. Number of states in an 8-bit Johnson counter sequence are:
a. 8
b. 12
c. 14
d.16
86. A synchronous decade counter will have flip-flops
a. 3
b.4
e. 7
f. 10
87. is one of the examples of synchronous
inputs
. a. J-K input
e. EN input
f. Preset input (PRE)
g. Clear input (CLR)
88. A decade counter is
a. Mod-3 counter
b. Mod-5 counter
c. Mod-8
counter d. Mod10 counter
89. is said to occur when multiple internal variables change due to change in one
input variable
a. Hold and Wait
b. Clock Skew
c. Race condition
d. Hold delay
90. In moore machine the output depends on
a. The current state and the output of previous flip flop
b. Only inputs
c. The current state
d. The current state and inputs
91. Asynchronous mean that
a. Each flip-flop after the first one is enabled by the output of the preceding flip-flop
b. Each flip-flop is enabled by the output of the preceding flip-flop
c. Each flip-flop except the last one is enabled by the output of the preceding flip-flop
d. Each alternative flip-flop after the first one is enabled by the output of the
preceding flip-flop
92. Bi-stable devices remain in either of their states unless the inputs force the device
to switch its state
a. Ten
b. Eight
c. Thr
ee
d. Two
93. A counter is implemented using three (3) flip-flops, possibly it will have
maximum output status.
a. 3
b. 7
c. 8
c. 15
94. According to moore circuit, the output of synchronous sequential circuit depend/s on
of flip flop.
a. Previous
state
b. Present state
e. Next state
f. External inputs
95. In gated SR latch, what is the value of the output if EN=1, S=0 and R=1?
a. Q
t
b.0
e. 1
f. Invalid
96. A Divide-by-20 counter can be achieved by
using
a. Flip-Flop and DIV 10
e. Flip-Flop and DIV 16
f. Flip-Flop and DIV 32
AL-JUNAID INSTITUTE GROUP
g. DIV 10 and DIV 16
97. We have a digital circuit. Different parts of circuit operate at different clock frequencies
(4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock
frequency (4MHZ), to supply the required frequency to each part of circuit, we can get
help by using
.
a. Using S-R Flop-Flop
b. D-flipflop
c. J-K flip-flop
d. T-Flip-Flop
98. A one-shot mono-stable device contains _
a. AND gate, Resistor, Capacitor and NOT Gate
b. NAND gate, Resistor, Capacitor and NOT
Gate
c. NOR gate, Resistor, Capacitor and NOT Gate
d. XNOR gate, Resistor, Capacitor and NOT Gate
99. The inputs can be directly mapped to karnaugh maps.
a. S
-R
b.J-K
e. Flip-Flop
f. External
100. A mono-stable device only has a single
stable state
a. True
b. False
101. The minimum time required for the
input logic levels to remain stable before the clock transition occurs is known as the
a. Set-up time
b. Hold time
c. Pulse interval time
d. Pulse stability time (PST)
102.
The low to high or high to low transition of the clock is considered to be a(n)
a. Sta
te
b.Edge
e. Trigger
f. One-shot
103. A 4-bit UP/DOWN counter is in DOWN mode and in the 1010 state, on the next clock
pulse, to what state does the counter go?
a. 1001
b. 1011
c. 0011
d. 1100
104. When the Hz sampling interval is selected, the signal at the output of
the J-K flip-flop has a time period of seconds.
a. 1, 2
b. 0, 2
c. 2, 5
d. 1, 1
105. Assume a J-K flip-flop has 1s on the J and K inputs. The next
clock pulse will cause the output to .
a. Set
b. Toggle
c. Latch
d. Reset
106. A stage in the shift register consists of
a. A latch
b. A flip flop
c. A byte of storage
d. Four bits of storage
107. When
the both inputs of edge-triggered J-K flop-flop are set to logic zero
a. The flop-flop is triggered
b. Q=0 and Q’=1
c. Q=1 and Q’=0
d. The output of flip-flop remains unchanged
108. A positive edgetriggered flip-flop changes its state when
a. Enable input (EN) is set
b. Preset input (PRE) is set
c. Low-to-high transition of clock
d. High-to-low transition of clock
109. If a circuit suffers “Clock Skew” problem, the output of circuit can’t be
guarantied.
a. True
b. False
110. The minimum time for which the input signal has to be maintained at the
input of flip-flop is called of the flip-flop.
a. Set-up
time
b. Hold time
e. Pulse interval time
AL-JUNAID INSTITUTE GROUP
f. Pulse stability time (PST)
111. A modulus-14 counter has
fourteen states requiring
a. 14 flip flops
b. 14
registers
c. 4 flip flops
d. 4 registers
112. In
Master-Slave flip-flop the clock signal is connected to slave flip-flop using gate.
a. AND
b. O
R
c.NOT
d. NAND
113. flip-flops are obsolete now.
a. Edgetriggered
b.Master-Slave
e. T-flipflop
f. D-flipflop
114. The operation of J-K flip-flop is similar to that of the SR flip-flop
except that the J-K flip flop
a. Doesn’t have an invalid state
b. Sets to clear when both J=0 and K=0
c. It does not show transition on change in pulse
d. It does not accept asynchronous inputs
115. The glitches
due to “Race Condition” can be avoided by using a .
a. Gated flip-flops
b. Pulse triggered flip-flops
c. Positive-Edge triggered flipflops
d. Negative-Edge triggered flip-flops
116. For a gated D-Latch if EN=1
and D=1 then Q(t+1)=
a. 0
b.1
e. Q(t)
f. Invalid
117. occurs when the same clock signal arrives at different times at
different clock inputs due to propagation delay.
a. Race condition
b.Clock skew
e. Ripple effect
f. None of given options
118. In a 4-bit binary counter, the next state after the terminal count in the DOWN mode is
a. 0000
b. 1111
c. 0001
d. 10000
119. A 4-bit binary UP/DOWN counter is in the binary state zero, the
next state in the DOWN mode is
a. 0001
b. 1111
c. 1000
d. 1110
120. An Astable multivibrator is known as a(n) .
a. Oscillator
e. Booster
f. One-shot
g. Dual-shot
121. is one of the examples of asynchronous inputs.
a. J-K input
b. S-R input
c. D input
d. Clear input (CLR)
122. In Master-Slave
flip-flop setup, the master flip-flop operators at
a. Positive half cycle of pulse
b. Negative half cycle of pulse
c. Both Master-Slave operator simultaneously
d. Master-Slave flip-flop does not operate on pulses rather it is edge triggered
123. The power consumed by a flipflop is defined by _
a. P = Icc x Rcc
b. P = Vcc x Rcc
c. P = Vcc x Icc
d. P = Mcc x Vcc
124. In designing any counter the transition from a current state to the next state is
determined by
a. Current state and inputs
e. Only inputs
f. Only current state
g. Current state and outputs
125. The 74HC163 is a 4-bit
Synchronous Counter, it has parallel data inputs pins
a. 2
b.4
e. 6
f. 8
126. The 3-bit up counter can be
implemented using flip-flop(s).
a. S-R flip-flops only
b. S-R flip-flops and D-flip-flops
c. S-R flip-flops or D-flip-flops
d. D-flip-flop only
127. The terminal count of a modulus-13 binary
counter is a. 0000
b. 1111
c. 1101
d. 1100
128. The terminal count of a 4-bit binary counter in the DOWN mode is
a. 0000
b. 0011
c. 1100
d. 1111
129. In gated SR latch, what is the value of the output if EN=1, S=1 and R=0?
a. Qt
b. 0
c.1
d. Invalid
130. In gated SR latch, what is the value of the output if EN=1, S=0 and
R=0?
a. Qt
e. 0
f. 1
g. Invalid
131. Which mechanism allocate the binary values to the states in order to reduce the cost
of the combinational circuits?
a. State reduction
b. State
minimization
c.State assignment
d. State evaluation
132. State of flip-flop can be switched by changing its
a. Input signal
e. Output signal
f. Momentary signal
g. Contemporary signal
133. Once the state diagram is drawn for any sequential circuit the next step is to draw
a. Transiation table
b. Karnaugh
map c. Next-state
table
c. Logic expression
134. Design of state diagram is one of many steps used to design
a. A clock
b. A truncated counter
c. An UP/DOWN counter
d. Any counter
135. Flip flops are also called
a. Bi-stable multivibrators
e. Bi-stable singlevibrators
f. Bi-stable dualvibrators
g. Bi-stable transformer
136. Three cascaded modulus-10 counters have an overall modulus of
a. 30
b. 100
c. 1000
d. 10000
137. In mealy machine the output depends on
a. The inputs
b. The current state
c. Current state and the inputs
d. None of the above
138. If S=1 and R=0, then for positive
edge triggered flip-flop Q(t+1) =
a. 0
b.
1
e. Invalid
f. Input is invalid
139. The term hold always means . a. Q=0, Q’=1
b. Q=1, Q’=0
c. Q=0, Q’=0
d. No change
140. A transparent mode means
a. The changes in the data at the inputs of the latch are seen at the output
b. The changes in the data at the inputs of the latch are not seen at the output
c. Propagation delay is zero (output is immediately changed when clock signal
is applied)
d. Input hold time is zero (no need to maintain input after clock ttransition)
141. A flip-flop is presently in SET state and must remain SET on the next clock pulse.
What must j and k be?
a. J=1, K=0
b. J=1, K=X(Don’t
care)
c. J=X(Don’t care), K=0
d. J=0, K=X(Don’t care)
142. To parallel load a byte of data into a shift register, there
must be
a. One clock pulse
e. One clock pulse for each 1 in the data
f. Eight clock pulse
g. One clock pulse for each 0 in the data
0 Comments